When designing an electronic system using available components, an incompatible signaling is sometimes encountered. One such problem is interfacing between single-transfer and burst-transfer components; A single transfer component is designed to send and receive one unit (typically one byte) of information at a time. A burst transfer component is designed to send and receive multiple unites, or typically multiple bytes, at a time. Since the manners of transfer are different for the two kinds of components, there are problems of incompatible timing and signaling, which can lead to loss of data or incorrect communication. The problem may be made even more complex if there is a packet exchange protocol involved, or if the signal lines of the components follow different conventions and protocols regarding the busy states of the components, etc. The present invention arose out of the above perceived needs and concerns associated with interfacing incompatible signaling between single-transfer and burst-transfer components.